[saboot]

This looks really cool. An application I would use this for is to generate code for FPGAs, as finite state machines are very common.

This is an example, https://terostechnology.github.io/terosHDLdoc/docs/guides/st...

But it only outputs an SVG, and there are no tools (AFAIK) that go from diagram to code, which should easy to setup.

So I'd consider extending this to both generate code and read in code and make these nice interactive diagrams.

[ttd]

Thank you for the feedback! This is a great idea and definitely fits into the vision.

Do you know if the FPGA and/or hardware communities use any type of formalism for design or documentation of state machines? One example of what I mean is is Harel statecharts - essentially a formalized type of nested state diagram.