top | item 44495633

(no title)

variaga | 7 months ago

Word. 28 years of FPGA and ASIC design here, in VHDL, Verliog and SystemVerliog. Coming from VHDL, verilog had some painful limitations (no struct/record type) but SV fixed those, and supports some surprisingly powerful metaprogramming.

But even when using plain verilog the language was never the limiting factor on the design process.

discuss

order

No comments yet.