top | item 44697119 (no title) arrakark | 7 months ago Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures. discuss order hn newest p_l|7 months ago 64 byte cache line size matches 64byte single burst transaction on DDR3-5, and ganged dual channel transaction on DDR2. Matching those together means you have a nice 1-to-1 relationship between filling a cache line and single fast memory transaction Dylan16807|7 months ago "Network on Chip" okay got it. crest|7 months ago A 64B cache-line is the same size as an AVX-512 register.
p_l|7 months ago 64 byte cache line size matches 64byte single burst transaction on DDR3-5, and ganged dual channel transaction on DDR2. Matching those together means you have a nice 1-to-1 relationship between filling a cache line and single fast memory transaction
p_l|7 months ago
Dylan16807|7 months ago
crest|7 months ago