PCIe 8.0 announced by the PCI-Sig will double throughput again

[SlightlyLeftPad]

Any EEs that can comment on at what point do we just flip the architecture over so the GPU pcb is the motherboard and the cpu/memory lives on a PCIe slot? It seems like that would also have some power delivery advantages.

[kvemkon]

> at what point do we just flip the architecture over so the GPU pcb is the motherboard and the cpu/memory

Actually the RapsberryPi (appeared 2012) was based on a SoC with a big and powerful GPU and small weak supporting CPU. The board booted the GPU first.

[verall]

If you look at a any of the nvidia DGX boards it's already pretty close.

PCIe is a standard/commodity so that multiple vendors can compete and customers can save money. But at 8.0 speeds I'm not sure how many vendors will really be supplying, there's already only a few doing serdes this fast...

[vincheezel]

Good to see I’m not the only person that’s been thinking about this. Wedging gargantuan GPUs onto boards and into cases, sometimes needing support struts even, and pumping hundreds of watts through a power cable makes little sense to me. The CPU, RAM, these should be modules or cards on the GPU. Imagine that! CPU cards might be back..

[0manrho]

We're already there. That's what a lot of people are using DPU's are for.

An example, This is storage instead of GPU's, but as the SSD's were PCIe NVMe, it's pretty nearly the same concept: https://www.servethehome.com/zfs-without-a-server-using-the-...

[bgnn]

EE here. There's no reason to not deliver power directly to the GPU by using cables. I'm not sure if it's sooving anything.

But you are right, there's no hierarchy in the systems anymore. Why do we even call something a motherboard? There's a bunch of chips interconnected.

[pshirshov]

Can I just have a backplane? Pretty please?

[dylan604]

Wouldn't that mean an complete mobo replacement to upgrade the GPU? GPU upgrades seem much more rapid and substantial compared to CPU/RAM. Each upgrade would now mean taking out the CPU/RAM and other cards vs just replacing the GPU

[MurkyLabs]

Yes I agree, let's bring back the SECC style CPU's from the Pentium Era, I've still got my Pentium II (with MMX technology)

[Dylan16807]

And limit yourself to only one GPU?

Also CPUs are able to make use of more space for memory, both horizontally and vertically.

I don't really see the power delivery advantages, either way you're running a bunch of EPS12V or similar cables around.

[mcdeltat]

Personally I hope this point comes after we realise we don't need 1kW GPUs doing a whole lot of not much useful

[burnt-resistor]

Figure out how much RAM, L1-3|4 cache, integer, vector, graphics, and AI horsepower is needed for a use-case ahead-of-time and cram them all into one huge socket with intensive power rails and cooling. The internal RAM bus doesn't have to be DDRn/X either. An integrated northbridge would deliver PCIe, etc.

[iszomer]

I wonder how many additional layers are required in the PCB to achieve this + how this will dramatically affect the TDP; the GPU's aren't the only components with heat tolerance and capacitance.

[j16sdiz]

It is not a EE problem. It is an ecosystem problem. You need a whole catalog of compatible hardware for this.

[coherentpony]

The concept exists now. You can "reverse offload" work to the CPU.

[Razengan]

Isn't that what has kinda sorta basically happened with Apple Silicon?

[leoapagano]

One possible advantage of this approach that no one here has mentioned yet is that it would allow us to put RAM on the CPU die (allowing for us to take advantage of the greater memory bandwidth) while also allowing for upgradable RAM.

[LeoPanthera]

Bring back the S100 bus and put literally everything on a card. Your motherboard is just a dumb bus backplane.

[bhouston]

I love the PCIe standard is 3 generations ahead of what is actually released. Gen5 is the live version, but the team behind it is so well organized that they have a roadmap of 3 additional versions now. Love it.

[zamadatix]

"3 generations" seems like a bit of a stretch. Millions of Blackwell systems use PCIe 6.x today, PCIe 7.x was finalized last month, and this is an announcement work on PCIe 8.0 has started for release in 3 years. I.e. it has only been one month of being one generation behind the latest PCIe revision.

It'll be interesting if consumer devices bother trying to stay with the latest at all anymore. It's already extremely difficult to justify the cost of implementing PCIe 5.0 when it makes almost no difference for consumer use cases. The best consumer use case so far is enthusiasts who want really fast NVMe SSDs in x4 lanes, but 5.0 already gives >10 GB/s for a single drive, even with the limited lane count. It makes very little difference for x16 GPUs, even with the 5090. Things always creep up over time, but the rate at which the consumer space creeps is just so vastly different from what the DC space has been seeing that it seems unreasonable to expect the two to be lockstep anymore.

[tails4e]

It takes a long time to get form standard to silicon, so I bet there are design teams working on pcie7 right now, which won't see products for 2 or more years

[Seattle3503]

Is there an advantage of getting so far ahead of implementations? It seems like it would be more difficult to incorporate lessons.

[ThatMedicIsASpy]

Gen6 is in use look at Nvidia ConnectX-8

[jsolson]

This actually makes sense from a spec perspective if you want to give enough to allow hardware to catch up with the specs and to support true interop.

Contrast this with the wild west that is "Ethernet" where it's extremely common for speeds to track well ahead of specs and where interop is, at best, "exciting."

[Phelinofist]

So we can skip 6 and 7 and go directly to 8, right?

[robotnikman]

I know very little about electronics design, so I always find it amazing that they keep managing to double PCIe throughput over and over. Its also probably the longest lived expansion bus at the moment.

[wmf]

It's less surprising if you realize that PCIe is behind Ethernet (per lane).

[rbanffy]

I’m sure you can get some VMEbus boards.

[zkms]

My reaction to PCIe gen 8 is essentially "Huh? No, retro data buses are like ISA, PCI, and AGP, right? PCIe Gen 3 and SATA are still pretty new...".

I wonder what modulation order / RF bandwidth they'll be using on the PHY for Gen8. I think Gen7 used 32GHz, which is ridiculously high.

[Dylan16807]

> PCIe Gen 3 and SATA are still pretty new...

That's an interesting thought to look at. PCIe 3 was a while ago, but SATA was nearly a decade before that.

> I wonder what modulation order / RF bandwidth they'll be using on the PHY for Gen8. I think Gen7 used 32GHz, which is ridiculously high.

Wikipedia says it's planned to be PAM4 just like 6 and 7.

Gen 5 and 6 were 32 gigabaud. If 8 is PAM4 it'll be 128 gigabaud...

[eqvinox]

I'd highly advise against using GHz here (without further context, at least), a 32Gbaud / 32Gsym/s NRZ signal toggling at full rate is only a 16GHz square wave.

baud seems out of fashion, sym/s is pretty clear & unambiguous.

(And if you're talking channel bandwidth, that needs clarification)

[weinzierl]

Don't forget VESA Local Bus.

[richwater]

Meanwhile paying a premium for a Gen5 motherboard may net you somewhere in the realm of 4% improvements in gaming if you're lucky.

Obviously PCI is not just about gaming but...

[simoncion]

From what I've seen, the faster PCI-E bus is important when you need to shuffle things in and out of VRAM. In a video game, the faster bus reduces the duration of stutters caused by pushing more data into the graphics card.

If you're using a new video card with only 8GB of onboard RAM and are turning on all the heavily-advertised bells and whistles on new games, you're going to be running out of VRAM very, very frequently. The faster bus isn't really important for higher frame rate, it makes the worst-case situations less bad.

I get the impression that many reviewers aren't equipped to do the sort of review that asks questions like "What's the intensity and frequency of the stuttering in the game?" because that's a bit harder than just looking at average, peak, and 90% frame rates. The question "How often do textures load at reduced resolution, or not at all?" probably requires a human in the loop to look at the rendered output to notice those sorts of errors... which is time consuming, attention-demanding work.

[checker659]

No matter the leaps in bandwidth, the latency remains the same. Also, with PCIe switches used in AI servers, the latency (and jitter) is even pronounced.

[jeffbee]

By an overwhelming margin, most computers are not in gamers' basements.

[LeoPanthera]

I thought we were only just up to 5? Did we skip 6 and 7?

[pshirshov]

Yeah, such a shame I've just upgraded to a 7.0 motherboard for my socket AM7 CPU.

Being less sarcastic, I would ask if 6.0 mobos are on the horizon.

[bpbp-mango]

I wonder if this will help applications like VPP/DPDK. not sure if the CPU or the lanes are the bottleneck there.

[top_sigrid]

For all the others seeing the HN Hugg of death :)

https://archive.is/oa81K

[ThatMedicIsASpy]

I'll take it if my consumer mb chipset supports giving me 48 PCIe7 lanes if future desktops still would only come with 24 gen 8 lanes

[iFred]

I can't be the only one let down that there wasn't some new slot design. Something with pizzazz and flare.

[_zoltan_]

what I don't get: why doesn't AMD just roll Gen6 out in their CPU, bifurcate it to Gen5, and boom, you have 48x2 Gen5s? same argument for gen5 bifurcated to gen4.

this would solve the biggest issue with non-server motherboards: not enough PCIe lanes.

[rfl890]

So I can run a full powered PCIe 4.0 16x GPU on 1 PCIe 8.0 lane???

[Melatonic]

I feel like what we really need is a GPU "socket" like we have for CPU's. And then a set of RAM slots dedicated to that GPU socket (or unified RAM shared between CPU and GPU)