[damageboy]

I work in NS. The riscv was the "one more thing" aspect of the "reveal".

The main product/architecture discussed has nothing to do with vector processors or riscv.

It's a new, fundamentally different data-flow processor.

Hopefully we will improve in explaining what we do and why people may want to care.

[joha4270]

So, a Systolic Array[1] spiced up with a pinch of control flow and a side of compiler cleverness? At least that's the impression I get from the servethehome article linked upthead. I wasn't able to find non-marketing better-than-sliced-bread technical details from 3 minutes of poking at your website.

[1]: https://en.wikipedia.org/wiki/Systolic_array

[damageboy]

I can see why systolic arrays come to mind, but this is different. While there are indeed many ALUs connected to each other in a systolic array and in a data-flow chip, data-flow is usually more flexible (at a cost of complexity) and the ALUs can be thought of as residing on some shared fabric.

Systolic arrays often (always?) have a predefined communication pattern and are often used in problems where data that passes through them is also retained in some shape or form.

For NextSilicon, the ALUs are reconfigured and rewired to express the application (or parts of) on the parallel data-flow acclerator.

[CheeseFromLidl]

Are the GreenArray chips also systolic arrays?

[slwvx]

Text on the front page of the NS website* leads me to think you have a fancy compiler: "Intelligent software-defined hardware acceleration". Sounds like Cerebras to my non-expert ears.

* https://www.nextsilicon.com

[damageboy]

No real overlap with Cerebras. Have tons of respect for what they do and achieve, but unrelated arch / approach / target-customers.