[eirikbakke]

In case anyone needs a minimal CPU implementation in 65 lines of Verilog: https://people.csail.mit.edu/ebakke/fic/ https://people.csail.mit.edu/ebakke/fic/code/Fic.v

(I wonder if it would convert cleanly to a redstone circuit...)

[lpribis]

This compiler does not support sequential logic, meaning no flip flops/registers.