[6SixTy]

They are basically acquiring talent and/or preexisting IP. RISC-V is free but implementations are the sole IP of the company.

Implementing ARM and RISC-V decoders might depend on licensing fine print for each licensee

[Zhyl]

This. SiFive, for example, is a proprietory core design based on the open source RISC V spec. Hazard3 [0] on the other hand, is an open source core design.

[0] https://github.com/Wren6991/Hazard3

[jrepinc]

Another opensource core design is XiangShan https://xiangshan.cc/en/

[disdi]

Another opensource is https://github.com/SpinalHDL/VexRiscv