It almost certainly refers to 300 mm wafers, which are the largest size used right now. They offer significantly better economics than the older 200 mm wafers or lab experiments done in even smaller (i.e. 100 mm) wafers.
The text in the article supports this:
> This is a commercial 300mm monolithic silicon photonics platform, meaning the technology is ready to scale today, rather than being limited to laboratory experiments.
> footprint of 330 × 290 µm2 using the GlobalFoundries 45SPCLO
That’s a 45nm process but the units for the chip size probably should have been 330um? However I’m not well versed enough in the details to parse it out.
I'm very familiar with this process as I use it regularly.
The area is massive. 330um × 290um are the X and Y dimensions. The area is roughly 0.1 mm2. You can see the comparison on table 1. This is roughly 50000 times larger than an SRAM of 45nm process.
This is the problem with photonic circuits. They are massive compared to electronics.
KK7NIL|2 months ago
The text in the article supports this:
> This is a commercial 300mm monolithic silicon photonics platform, meaning the technology is ready to scale today, rather than being limited to laboratory experiments.
vlovich123|2 months ago
> footprint of 330 × 290 µm2 using the GlobalFoundries 45SPCLO
That’s a 45nm process but the units for the chip size probably should have been 330um? However I’m not well versed enough in the details to parse it out.
https://arxiv.org/abs/2503.19544
bgnn|2 months ago
The area is massive. 330um × 290um are the X and Y dimensions. The area is roughly 0.1 mm2. You can see the comparison on table 1. This is roughly 50000 times larger than an SRAM of 45nm process.
This is the problem with photonic circuits. They are massive compared to electronics.