[barchar]

This is not always true. Compilers are quite good at register allocation but sometimes they get it wrong and sometimes you can make small changes to code that improve register allocation and thus performance.

Usually the problem is an unfortunately placed spill, so the operation is actually l1d$ traffic, but still.

[zahlman]

> l1d$

I don't know how to interpret this.

[andrewf]

Level 1 data cache