[skinwill]

How deep down the rabbit hole did you go with hardware optimization?

In an ideal world, would it be better to compile this on a processor more RISC-y?

[krish678]

Thanks for asking! So far, optimizations are on x86—CPU pinning, NUMA layouts, huge pages, and custom NIC paths. Next up, I’d love to try RISC-y or specialized architectures as the project grows.

The focus is still on learning and pushing latency on regular hardware.