[xerxes901]

Something like the stm32mp2 series of MCUs can run Linux and act as a PCIe endpoint you can control from a kernel module on the MCU. So you can program an arbitrary PCIe device that way (although it won’t be setting any speed records, and I think the PHY might be limited to PCIe 1x)

[jdub]

(Ha, nice to see Jon Corbet's name on the PCI Endpoint documentation...)

[tiernano]

interesting... x1 would too slow for large amounts of storage, but as a test, a couple small SSDs could potentially be workable... sounds like im doing some digging...

[jacquesm]

There are many workloads that would not be able to saturate even an x1 link, it all depends on how much of the processing can be done internally to whatever lives on the other side of that link. Raw storage and layer-to-layer communications in AI applications are probably the worst cases but there are many more that are substantially better than that.

[cakehonolulu]

If there's any particular feature you feel you are missing on PCIem or anything, feel free to open an Issue and I'll look into it ;)