[lesser-shadow]

As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will. SDF-annotated simulation actually shows data hazards, as well as transistor timings.

https://librelane.readthedocs.io/en/latest/usage/timing_clos...

[random_duck]

> Once again, I used Cocotb as the abstracting layer allowing me to interface with multiple different simulators. Namely, icarus verilog for my standard verification and CVC for the post implementation timing annotated netlist.