[labcomputer]

Is that actually true for SSDs? I was under the impression that manufacturers have a speed-capacity tradeoff "knob" they can adjust.

Specifically, that each buried gate can store one bit (SLC), two bits (MLC), three bits (TLC) or even more.

Obviously more bits means closer thresholds, making the gate more susceptible to electrical noise when reading and writing (and process variation in the dopant loading).

It's pretty easy to think up ways to pack in more bits that would slow down the read rate... such as applying multi-level ECC or just waiting longer for the read ADCs to settle.