[geokon]

On a high level, do I understand correctly that SIMD is close to how the hardware works, while Vector Processor is more of an abstraction? The "Strip Mining" part looks like this translation to something SIMD-like. I seems like it's a good abstraction layers, but there is an implicit compilation step right? (making the "assembly" more easily run on different actual hardware)

[Someone]

> On a high level, do I understand correctly that SIMD is close to how the hardware works, while Vector Processor is more of an abstraction?

Not quite. It still is the same “process whatever number of items you can in parallel, decrease count by that, repeat if necessary“ loop.

RISC-V decided to move the “decrease count by that, repeat if necessary” part into hardware, making the entire phrase “how the hardware works”.

Makes for shorter and nicer assembly. SIMD without it first has to query the CPU to find out how much parallelization it can handle (once) and do the “decrease count by that, repeat if necessary” part on the main CPU.

[dzaima]

RVV still very much requires you to write a manual code/assembly loop doing the "compute how many elements can be handled, decrease count by that, repeat if necessary" thing. All it does is make it slightly less instructions to do so (and also allows handling a loops tail in the same loop while at it).

[geokon]

I mean, "move in to hardware" is effectively more of a micro code translation/compilation step right? The actual silicon implementation of how things are in-the-end going to be executed on the silicon is not fundamentally rearchitected right?

I'm going to try to read through the full document carefully later :)) Likely it's answered in there