What you describe sounds counter-intuitive. And the paper you cite seems to suggest an ISA extension to increase the number architected (!) registers. That is something very different. It makes most sense in VLIW architectures, like the ones described in the paper. Architectures like x86 do hardware register renaming (or similar techniques, there are several) to be able to exploit as much instruction level parallelism as possible. That is why I find you claim hard to believe. VLIW architectures traditionally provide huge register sets and make less use of transparent register renaming etc, that part is either explicit in the ISA or completely left to the compiler. These are very different animals than our good old x86...
solarexplorer|14 days ago
noelwelsh|14 days ago
https://smlnj.org/compiler-notes/k32.ps
E.g. "Our strategy is to pre-allocate a small set of memory locations that will be treated as registers and managed by the register allocator."
There are more recent publications on "compiler controlled memory" that mostly seem to focus on GPUs and embedded devices.