top | item 47112145 (no title) sitkack | 7 days ago The ESP32 pre-RISCV ISA is from Tensilica, this IP they purchased. discuss order hn newest Kiboneu|6 days ago To be clear and towards the OP's comment about ESP32 ISA -- Xtensa isn't really a self contained architecture, it can be customized (extended) by the vendor. The ISA can be extended for these customizations. ESP32 is one customization of it. sitkack|6 days ago It was only opaquely supported by GCC, no LLVM, so no Rust.It is a cool design, but it was a major PITA for awhile. Xtensa is parametric so every instance of a cpu has a custom instruction set. load replies (1)
Kiboneu|6 days ago To be clear and towards the OP's comment about ESP32 ISA -- Xtensa isn't really a self contained architecture, it can be customized (extended) by the vendor. The ISA can be extended for these customizations. ESP32 is one customization of it. sitkack|6 days ago It was only opaquely supported by GCC, no LLVM, so no Rust.It is a cool design, but it was a major PITA for awhile. Xtensa is parametric so every instance of a cpu has a custom instruction set. load replies (1)
sitkack|6 days ago It was only opaquely supported by GCC, no LLVM, so no Rust.It is a cool design, but it was a major PITA for awhile. Xtensa is parametric so every instance of a cpu has a custom instruction set. load replies (1)
Kiboneu|6 days ago
sitkack|6 days ago
It is a cool design, but it was a major PITA for awhile. Xtensa is parametric so every instance of a cpu has a custom instruction set.