It might not end up with the hoped for performance per watt -- or even with all that good performance, period. It might not even be built in silicon.
But it is a damn interesting architecture.
You don't get to present bits and pieces of it over several EE380 talks unless the grownups think it is interesting, too.
(It is also a lot less like the Itanic than it initially seemed. I think we will know a lot more in about a month, since there will be a new talk in Amsterdam about the new vector model and their µthreading model.)
We do not have an FPGA implementation, although we are working on it.
The reason getting to product is slow is that we are by choice a bootstrap startup, with three full-timers and a dozen or so part-timers. Compare a CPU project at a major such as Intel or ARM, with hundreds of full-time engineers, big budgets, and five years of development before the product is even announced - all for minor modifications to an established and well understood design.
The Mill architecture is notable primarily in what it takes out of the CPU, rather than what it puts in.
Patents are a backbreaking amount of work. To economize in filing costs our attorneys have consolidated what we expected to be separate patents into single filings - no less work, just fewer/bigger and hence cheaper. So far the twenty filings that have gone in represent around two thirds of the core technology. And if you think that 80-odd pages of patentese is fun then you are more kinky than should be let out in public.
"Architecture astronaut" is a cute term, not restricted to architecture; I have more than enough experience with those full of ideas - for someone else to do. We have done a lot of architecture over the decade, but a fair amount of work too. For a live demo the result of some of our work see http://millcomputing.com/docs/specification/
While I have worked in academia, I am more comfortable in an environment making real things for real people (or trying to) rather than sheepskins.
The purpose of our talks is to get professional validation of the design in a way we can afford. It is not to sell you something; it will be quite a while before we have something to sell, and you are not our customer.
We have a private placement in process and welcome Reg-D qualified investors. If you do not know what that is then you probably aren't. For details: http://millcomputing.com/investor-list. We are not cruising Sand Hill Road. We estimate ~$6M to an FPGA, and $25M to a product. Heavy semi is serious industry.
In early days I did my first compiler for a Bob Barton-designed machine, the Burroughs B6500. That compiler is still in use forty five years later. I wish Barton were still here today; the Mill owes a great deal to his design philosophy.
The most interesting thing I took from the Mill videos I watched is the way they define the processor features in code. They can describe the whole specification in code, compile and test the CPU. Then get enough information from the simulation to actually put together the layout for the physical cpu. You can add or remove features from the CPU by implementing the proper functions, and test the specification before committing to silicon. My background is software, so maybe it's not as impressive as it sounds, but it really caught my ear as an elegant solution to customizing a processor architecture for different needs.
I really hope that mills go into production. One thing that current comments have not mentioned is that there are huge security wins using a mill. Even if there are concerns about performance I think that the security architecture has use cases that will see mills brought into production.
The original of this discussion was a blog post on kevmod.com. I posted the following comment on that blog, repeated here verbatim as possibly of general interest:
++++++++++++++++++++++++++++++++++++++++++++++++++++
Your skepticism is completely justified. The Mill may never reach market – we are a startup, and most startups fail; its a fact of life. Although we’ve survived for over a decade, which is pretty good for startups these days.
But it sounds like you are less skeptical about Mill Computing the company, but more about Mill the technology and architecture. There are fewer ground to doubt that. As fast as we have been able to get the patents filed (I seem to have been doing nothing else for the last two years. I hate patents) we have been completely opening the kimono and showing the technical community, in detail, how each part works. Why? because we wanted outside validation before wasting another decade in something that was fatally flawed in some way we had overlooked.
If there was any part of the public Mill that one could point at and say “See? that won’t work, because …” then the web would have been all over us. Buy you know? Skepticism we get, aplenty. What we don’t get is informed skepticism. In fact, the more senior and skilled the commenter, the more they fall in love with the design. Like Andy Glew said one time (and if you don’t know who that is then you are not in the CPU business) – “Yeah, it’ll work, just the way he says it will”.
Sometimes people complain that our presentations are insufficiently detailed to fairly evaluate. Guilty as charged; they are oriented for a high level audience interested in the subject, but not for the specialist. However, if you ask for details on our forum (mill computing.com/forum/themill) or the comp.arch newsgroup, as hundreds have, you will get all the details you want until they flood out your ears and collect in puddles on the floor.
In these days of internet time, when idea to market is measured in days or weeks, it’s east to forget that not all the economy works that way. Building steel mills, cement plants, and yes, CPU silicon takes a long time and a lot of money. We have deliberately swapped money for time: we are a bootstrap startup, not looking for VC funding. There’s good and bad in that choice: a decade without a paycheck is not easy, but today we own it – all of it – and feel we got a good deal.
The proof of the Mill pudding will be when there’s a product with pins on the bottom, and that won’t happen for some years yet. We learned in our first presentation not to make projections of what the eventual chip will have for numbers. Yes, we have guesstimates internally, but we’re quite sure those will be off by a factor of two. The problem is that we have no clue which direction they will be off.
If you have the technical chops to understand a CPU design from first principles then please dig as deep as you can into our stuff and tell us – and the world – what you find. Otherwise you will just have to join us as we wait and work and see. We’ve never said anything different.
I suspect that they have versions of it running in FPGAs but they aren't releasing anything to a wider audience because it's an FPGA and probably 5-50x slower than it would be if it was in custom silicon.
So it's incredibly useful for them to test out ideas, but would probably garner a lot of bad impressions even if you explain "look this is super slow" because people have the idea that revolutionary is supposed to be extra fast, extenuating circumstances be damned.
I think I remember them saying either in one of the talks or in a comment somewhere (sorry I can't be more specific), that, yes, they do have it working on an FPGA, but since the purpose is only to test the design, it doesn't run anything like impressively fast, because they aren't utilizing the resources efficiently.
EDIT: by resources, I mean, the specialized logic and chunks of RAM that exist inside FPGAs.
On the other hand, their wiki does have a lot of extremely interesting details about the processor and ISA design, and they have presented several concrete examples of how to get around the problems with Itanium.
It would be nice to hear from some more people in the industry about it, or see some more results, but I remain cautiously optimistic.
I have the same impression as you and commented here a while back. I think the answer to your question falls somewhere in the middle.
They are smart guys with interesting ideas, but will not be buying fab capacity or selling products anytime soon or most likely ever.
However there is a lot of value in provocative thinking. It adds to the collective knowledge and inspires new perspectives and approaches to problem solving. That alone makes me glad their around.
On the high end of expectations they may sell some patents or license some IP, but still not in the form of a complete or competitive product.
I've subscribed to the hype, but my knowledge of the domain is near zilch. It would definitely be interesting to hear a high level engineer at a company like Intel or ARM comment on the design.
They don't necessarily believe that it will succeed or that the whole architecture is good -- but the consensus seems to be that it at least is interesting.
Last I heard, they've been spending most their time getting patents filed since the US switched to first-to-file in 2011. There might be more physical progress once that's done, or so I hope.
I filed the Mill CPU under "call me when you ship" quite a while ago, because the constant "let me tell you how we will solve that with Mill" threat-squats got really old and in 30 years of doing this I've seen way to many "no, really, this is going to change all of computing as we know it" architectures proposed, that never amounted to anything worthwhile, and here in 2015 I'm still buying the 8086's grandkid. At least ARM and MIPS are keeping it somewhat interesting, and Power 7 and T5 are looking at interesting architecture innovations, and, most importantly, are actually shipping something instead of hanging out on HN telling us how awesome it will be one day.
I'm interested to see how a compiler for the Mill CPU would handle such large instruction widths. Whilst it doesn't have the restriction VLIW had of having a fixed instruction width, I'm not entirely convinced we would often see 30+ operations packed in the same instruction.
I have watched most of the Mill videos, and while they are certainly impressive and innovative, I believe Ivan Godard is a perpetual non-finisher. He comes up with grandiose complicated ideas, which turn out incredibly difficult to implement, debug, and close. And by the time he makes much progress, he has another idea that takes his focus, and starts working on that. He has these massive goals, which are certainly noteworthy, but possibly does not realize it's likely not possible to do them in one step.
You have to release incrementally, get something out the door, and then move to the next. Not "Let's design and architect a complete ASIC from scratch, based on an architecture from scratch, using a prototype simulator from scratch, with a toolchain built from scratch, with a new ABI for Linux, and a complicated debugger. Oh, and this is actually a family of processors (low perf/high perf), not just a single processor we are building."
It's the opposite of MVP. If he really wanted to make progress, he would find a way to incrementally build one piece of his suite of technology IP that he can license to existing CPU manufacturers and get into production. Then you have revenue, and can rinse and repeat. Otherwise the Mill as vaporware is a virtual certainty.
You do need feedback, lots of it, but not necessarily from customers. It is not a social media platform on the web using the hottest new framework. Your feedback mostly consists of numbers from measurements. That's why they built a simulator first (and it has apparently been running for quite some time). That's also why they did work on a compiler that they did get something useful out of (they have since switched their compiler approach to making an LLVM backend instead).
But getting to a point where you can run it in silicon (even just as an FPGA) is a long, tough slog. Especially if you want decent/realistic speed. Getting good numbers on power use is also both hard and expensive.
And it's all worth nothing if they don't have the patents. And many of the innovations need the other innovations to be useful or even just make sense.
I met both Ivan and a German guy who works on the compiler late last year and have corresponded a bit with both. What I have seen so far fits very well together... but of course there are still many pieces that they haven't shown (and that I haven't seen either).
Obviously this was written from a software engineering perspective, but it seems at least marginally fitting, as the topic in question is literally computer architecture.
This feels uncomfortably close to a personal attack.
Not everything can be built via MVP-and-iterate. How much further could a project be from the MVP-and-iterate sweet spot than a brand new CPU architecture?
People should be free to try wild new things, whether they succeed or not. A strong visionary, once at speed, won't be stopped by nitpicking comparison to less ambitious things. But I worry about how many nascent visionaries we miss out on when the culture trains us to disparage those impulses in ourselves, and so many people tell you you're doing it wrong.
[+] [-] peterfirefly|11 years ago|reply
But it is a damn interesting architecture.
You don't get to present bits and pieces of it over several EE380 talks unless the grownups think it is interesting, too.
(It is also a lot less like the Itanic than it initially seemed. I think we will know a lot more in about a month, since there will be a new talk in Amsterdam about the new vector model and their µthreading model.)
[+] [-] igodard|11 years ago|reply
We do not have an FPGA implementation, although we are working on it.
The reason getting to product is slow is that we are by choice a bootstrap startup, with three full-timers and a dozen or so part-timers. Compare a CPU project at a major such as Intel or ARM, with hundreds of full-time engineers, big budgets, and five years of development before the product is even announced - all for minor modifications to an established and well understood design.
The Mill architecture is notable primarily in what it takes out of the CPU, rather than what it puts in.
Patents are a backbreaking amount of work. To economize in filing costs our attorneys have consolidated what we expected to be separate patents into single filings - no less work, just fewer/bigger and hence cheaper. So far the twenty filings that have gone in represent around two thirds of the core technology. And if you think that 80-odd pages of patentese is fun then you are more kinky than should be let out in public.
"Architecture astronaut" is a cute term, not restricted to architecture; I have more than enough experience with those full of ideas - for someone else to do. We have done a lot of architecture over the decade, but a fair amount of work too. For a live demo the result of some of our work see http://millcomputing.com/docs/specification/
While I have worked in academia, I am more comfortable in an environment making real things for real people (or trying to) rather than sheepskins.
The purpose of our talks is to get professional validation of the design in a way we can afford. It is not to sell you something; it will be quite a while before we have something to sell, and you are not our customer.
We have a private placement in process and welcome Reg-D qualified investors. If you do not know what that is then you probably aren't. For details: http://millcomputing.com/investor-list. We are not cruising Sand Hill Road. We estimate ~$6M to an FPGA, and $25M to a product. Heavy semi is serious industry.
In early days I did my first compiler for a Bob Barton-designed machine, the Burroughs B6500. That compiler is still in use forty five years later. I wish Barton were still here today; the Mill owes a great deal to his design philosophy.
Ivan
[+] [-] ubercore|11 years ago|reply
http://millcomputing.com/docs/specification/
[+] [-] rasz_pl|11 years ago|reply
https://www.youtube.com/watch?v=3MghYhf-GhU
[+] [-] pkaye|11 years ago|reply
[+] [-] hyperion2010|11 years ago|reply
[+] [-] igodard|11 years ago|reply
But it sounds like you are less skeptical about Mill Computing the company, but more about Mill the technology and architecture. There are fewer ground to doubt that. As fast as we have been able to get the patents filed (I seem to have been doing nothing else for the last two years. I hate patents) we have been completely opening the kimono and showing the technical community, in detail, how each part works. Why? because we wanted outside validation before wasting another decade in something that was fatally flawed in some way we had overlooked.
If there was any part of the public Mill that one could point at and say “See? that won’t work, because …” then the web would have been all over us. Buy you know? Skepticism we get, aplenty. What we don’t get is informed skepticism. In fact, the more senior and skilled the commenter, the more they fall in love with the design. Like Andy Glew said one time (and if you don’t know who that is then you are not in the CPU business) – “Yeah, it’ll work, just the way he says it will”.
Sometimes people complain that our presentations are insufficiently detailed to fairly evaluate. Guilty as charged; they are oriented for a high level audience interested in the subject, but not for the specialist. However, if you ask for details on our forum (mill computing.com/forum/themill) or the comp.arch newsgroup, as hundreds have, you will get all the details you want until they flood out your ears and collect in puddles on the floor.
In these days of internet time, when idea to market is measured in days or weeks, it’s east to forget that not all the economy works that way. Building steel mills, cement plants, and yes, CPU silicon takes a long time and a lot of money. We have deliberately swapped money for time: we are a bootstrap startup, not looking for VC funding. There’s good and bad in that choice: a decade without a paycheck is not easy, but today we own it – all of it – and feel we got a good deal.
The proof of the Mill pudding will be when there’s a product with pins on the bottom, and that won’t happen for some years yet. We learned in our first presentation not to make projections of what the eventual chip will have for numbers. Yes, we have guesstimates internally, but we’re quite sure those will be off by a factor of two. The problem is that we have no clue which direction they will be off.
If you have the technical chops to understand a CPU design from first principles then please dig as deep as you can into our stuff and tell us – and the world – what you find. Otherwise you will just have to join us as we wait and work and see. We’ve never said anything different.
Ivan
[+] [-] msandford|11 years ago|reply
So it's incredibly useful for them to test out ideas, but would probably garner a lot of bad impressions even if you explain "look this is super slow" because people have the idea that revolutionary is supposed to be extra fast, extenuating circumstances be damned.
[+] [-] DanWaterworth|11 years ago|reply
EDIT: by resources, I mean, the specialized logic and chunks of RAM that exist inside FPGAs.
Found it: https://groups.google.com/forum/#!topic/comp.arch.fpga/BTojR...
[+] [-] Rusky|11 years ago|reply
It would be nice to hear from some more people in the industry about it, or see some more results, but I remain cautiously optimistic.
[+] [-] WhitneyLand|11 years ago|reply
They are smart guys with interesting ideas, but will not be buying fab capacity or selling products anytime soon or most likely ever.
However there is a lot of value in provocative thinking. It adds to the collective knowledge and inspires new perspectives and approaches to problem solving. That alone makes me glad their around.
On the high end of expectations they may sell some patents or license some IP, but still not in the form of a complete or competitive product.
[+] [-] saosebastiao|11 years ago|reply
[+] [-] peterfirefly|11 years ago|reply
Names to look for, apart from Ivan Godard, are Andy Glew, Mitch Alsup, and Terje Mathisen.
https://www.linkedin.com/in/andyglew
https://www.linkedin.com/pub/mitch-alsup/7/153/869
https://www.linkedin.com/pub/terje-mathisen/1/18/b74
They don't necessarily believe that it will succeed or that the whole architecture is good -- but the consensus seems to be that it at least is interesting.
[+] [-] agumonkey|11 years ago|reply
[+] [-] nshepperd|11 years ago|reply
[+] [-] kjs3|11 years ago|reply
[+] [-] pjmic|11 years ago|reply
[+] [-] jesstaa|11 years ago|reply
Most of the rest of the CPU design is really just to enable this.
[+] [-] unknown|11 years ago|reply
[deleted]
[+] [-] pdq|11 years ago|reply
You have to release incrementally, get something out the door, and then move to the next. Not "Let's design and architect a complete ASIC from scratch, based on an architecture from scratch, using a prototype simulator from scratch, with a toolchain built from scratch, with a new ABI for Linux, and a complicated debugger. Oh, and this is actually a family of processors (low perf/high perf), not just a single processor we are building."
It's the opposite of MVP. If he really wanted to make progress, he would find a way to incrementally build one piece of his suite of technology IP that he can license to existing CPU manufacturers and get into production. Then you have revenue, and can rinse and repeat. Otherwise the Mill as vaporware is a virtual certainty.
[+] [-] peterfirefly|11 years ago|reply
You don't build bridges like that, do you? Or skyscrapers?
What's the minimum viable product for something like this:
http://en.wikipedia.org/wiki/Great_Belt_Fixed_Link
http://en.wikipedia.org/wiki/Millau_Viaduct
You do need feedback, lots of it, but not necessarily from customers. It is not a social media platform on the web using the hottest new framework. Your feedback mostly consists of numbers from measurements. That's why they built a simulator first (and it has apparently been running for quite some time). That's also why they did work on a compiler that they did get something useful out of (they have since switched their compiler approach to making an LLVM backend instead).
But getting to a point where you can run it in silicon (even just as an FPGA) is a long, tough slog. Especially if you want decent/realistic speed. Getting good numbers on power use is also both hard and expensive.
And it's all worth nothing if they don't have the patents. And many of the innovations need the other innovations to be useful or even just make sense.
I met both Ivan and a German guy who works on the compiler late last year and have corresponded a bit with both. What I have seen so far fits very well together... but of course there are still many pieces that they haven't shown (and that I haven't seen either).
[+] [-] ohazi|11 years ago|reply
Edit: Apparently this is where I heard the term: http://www.joelonsoftware.com/articles/fog0000000018.html
Obviously this was written from a software engineering perspective, but it seems at least marginally fitting, as the topic in question is literally computer architecture.
[+] [-] dang|11 years ago|reply
Not everything can be built via MVP-and-iterate. How much further could a project be from the MVP-and-iterate sweet spot than a brand new CPU architecture?
People should be free to try wild new things, whether they succeed or not. A strong visionary, once at speed, won't be stopped by nitpicking comparison to less ambitious things. But I worry about how many nascent visionaries we miss out on when the culture trains us to disparage those impulses in ourselves, and so many people tell you you're doing it wrong.
[+] [-] yuhong|11 years ago|reply
[+] [-] jodrellblank|11 years ago|reply
[+] [-] JohnBooty|11 years ago|reply
[deleted]
[+] [-] Corporate_Shill|11 years ago|reply
[deleted]
[+] [-] cbd1984|11 years ago|reply
[+] [-] psykovsky|11 years ago|reply