[sigterm]

I am a pretty junior ASIC engineer who has relatively more exposure to software world compared to many of my peers.

In my last project I did some IP integration work and the lack of decent development tools led to significant chores. I did make use of Emacs verilog-mode like GP mentioned and even wrote some small macros in elisp but overall experience is far from satisfactory. Not to even mention the usability of propriety EDA tools and flows. The software world just looks like heaven with so many awesome development tools available (VS, PyCharm, intelliJ, to name a few I've used). And I can tell the difference because I once managed to convert a C# GUI software into a console application mainly with the help of an IDE (Visual Studio), without first learning C#.

Sadly, I think ASIC (or maybe broader, hardware) industry has a pretty poor ecosystem in general. I'm not aware of good hardware focused community comparable to HN, no high quality active Q&A on sites like stackoverflow; even the HDL languages look inelegant and not well thought out. And you have a point, I'm not even sure how many of my colleagues realize that. I want to make some difference. But I'm not sure where to start...

[adwn]

> I want to make some difference. But I'm not sure where to start...

1. Take a promising language, improve it where necessary.

2. Add excellent support for translation to VHDL and Verilog. The generated HDL code has to be readable, editable, and it has to reflect the structure of the original code more or less 1:1. You also need to support "inline VHDL/Verilog" (like inline assembly in software). Otherwise, your language doesn't integrate into the ecosystem of synthesis software, simulators, vendor-dependent Map/P&R, and existing IP cores, which makes it useless in the real world. This is the main reason why all innovative VHDL/Verilog replacements have failed so far. Without this feature, there's just no way your language is going to gain any significant market share.

[sigterm]

Are you referring to a new DSL based on software languages, something like MyHDL? I think this is definitely promising for designs that are started from scratch. However, as soon as there is need to integrate with other legacy code, it falls back to the current painful way of manual integration.

What do you think about an IDE that supplements existing HDL languages? Not as drastic as making a shiny new language, but it avoids many challenges you brought up.

Since you are coming from a CS background, do you have recommendation for good IDE frameworks that can be leveraged?

[MootWoop]

2. I am curious to hear what you think about our solution of wrapping existing VHDL/Verilog in an external task in Cx? http://cx-lang.org/documentation/tasks#external