mithro | 5 months ago | on: Wafer.space – $7k USD for 1k custom chips
mithro's comments
mithro | 8 months ago | on: The era of full stack chip designers
Things like my https://wafer.space ($7k USD), TinyTapeout.com (<$200 USD) and ChipFoundry.io (~$15k USD) are making it much cheaper to do IC design.
There are a huge number of designs from Tiny Tapeout which are all public - see https://tinytapeout.com/runs/
The designs are still more in the MCU size, but you have to start somewhere!
The Google open MPW program also had 10 runs with 40 projects published at http://foss-eda-tools.googlesource.com/third_party/shuttle/ -- All the submissions had to be open source and there were 1000+ of those. I did try pitching to multiple Google Research groups that continuing the open MPW funding would grow the available designs which have been manufactured and that was useful for AI training but didn't get any bites.
The now defunct Efabless also ran a number of challenges in this space which got pretty good results, see https://efabless.com/challenges
mithro | 8 months ago | on: The era of full stack chip designers
There is plenty of updates on the website at https://theopenroadproject.org/ - Including a pretty good report on what happened in 2024.
Also take a look at the Open Source EDA BOF from the DAC conference - https://open-source-eda-birds-of-a-feather.github.io/
mithro | 2 years ago | on: Signal reflections in electronic circuits
The team at Antmicro put together this pretty cool visualisation flow for this stuff using only open source tools -> https://antmicro.com/blog/2023/11/open-source-signal-integri...
mithro | 3 years ago | on: Tomu – A family of devices which fit inside your USB port
mithro | 3 years ago | on: Tomu – A family of devices which fit inside your USB port
I also have a general offer to send people who contribute to the open source FPGA tooling and ecosystem free Fomu boards.
mithro | 3 years ago | on: Tomu – A family of devices which fit inside your USB port
The Tomu family also has;
- The Fomu (FPGA Tomu) - https://fomu.im/ and https://workshop.fomu.im/
- The Qomu (ARM+eFPGA Tomu) - https://tomu.im/qomu.html
- The Somu (Secure Tomu) - https://www.crowdsupply.com/solokeys/somu
The Fomu is also a great RISC-V MCU prototyping platform.
mithro | 3 years ago | on: NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop
I afraid I don't recall the status of DSP blocks in the open source toolchains for Xilinx hardware. Even if the basics are supported I'm sure there are plenty of DSP features that are not.
Many configurations of VexRISCV work fine without using the DSP blocks (and has been working for 2+ years), so not sure that is relevant.
mithro | 3 years ago | on: NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop
I have a Google Doc at <https://j.mp/softcpus-on-fpgas> which includes a bunch of information about what type of performance has been achieved on modern Xilinx FPGAs.
You can generally do quite a bit of parallelism, see the quad-core LiteX+VexRISCV solution at <https://antmicro.com/blog/2020/05/multicore-vex-in-litex/>.
mithro | 3 years ago | on: NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop
The open source toolchain doesn't quite support the PCIe interface yet but all the other stuff should work in theory.
The best place to see what works is the F4PGA examples documentation at <https://f4pga-examples.readthedocs.io/en/latest/building-exa...>.
If you want to start with fully open source tools on a Xilinx 7 series FPGA the best option is the Digilent Arty A35T board <https://digilent.com/shop/arty-a7-artix-7-fpga-development-b...>.
mithro | 3 years ago | on: NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop
When did you last check? The Yosys+VPR toolchain currently supports a full Linux capable SoC with Ethernet and DDR memory on the Arty A35T (which has a Xilinx Artix 7 part), see the example at https://f4pga-examples.readthedocs.io/en/latest/building-exa...
mithro | 3 years ago | on: Ask HN: Are there any companies that are doing interesting work in hardware?
While the news seems to focuses on ML and RISC-V, there is a huge amount of *other* activity in the silicon space. With [Google working to improve the open source EDA tools + PDKs while also providing free manufacturing](https://opensource.googleblog.com/2022/05/Build%20Open%20Sil...) there are lots of opportunities.
The "new" FPGA companies like GowinSemi and RapidSilicon are also creating some pretty cool parts.
mithro | 4 years ago | on: VRoom A high end RISC-V implementation
Checkout Surelog - https://antmicro.com/blog/2020/12/ibex-support-in-verilator-... and the more recent usage in https://github.com/siliconcompiler/siliconcompiler
mithro | 4 years ago | on: FPGA Interchange format to enable interoperable FPGA tooling
On a semi-related note, Google has also been investigating in improving support for SystemVerilog support in open source tooling -> https://opensource.googleblog.com/2021/09/open-source-system...
mithro | 4 years ago | on: FPGA Interchange format to enable interoperable FPGA tooling
All these are good points but missed a key thing.
The interchange format includes a computer readable description of the FPGA which tells the tooling what is available inside the FPGA and how they can be connected.
mithro | 4 years ago | on: FPGA Interchange format to enable interoperable FPGA tooling
Except that nextpnr is one of the tools supporting the interchange format and you can see the status at https://symbiflow.github.io/fpga-interchange-tests/
mithro | 4 years ago | on: Renesas introduces sub 50 cents FPGA family with Yosys-based development tools
Project F (https://projectf.io/posts/fpga-graphics/) has a lot of cool examples with visually interesting output.
mithro | 4 years ago | on: Renesas introduces sub 50 cents FPGA family with Yosys-based development tools
If you are motivated by learning rather than practical usage, FPGAs are a great way to learn more about how things like CPUs or peripherals can be designed. It is also a way to understand how to evolve hardware and software at the same time.
Two examples that I have been loosely involved with; * Google's CFU playground which is all about profiling and adding small number of new OpCodes to build an accelerator for a specific ML model (http://cfu-playground.rtfd.io/). * The Fomu workshop (https://workshop.fomu.im) which walks though treating an FPGA like an embedded MCU where you can then modify the MCU!
mithro | 4 years ago | on: DDR4 memory protections are broken wide open by new Rowhammer technique
Google has been working on solutions to make it easier to explore this type of issue (and mitigation techniques), see https://opensource.googleblog.com/2021/11/Open%20source%20DD...
mithro | 4 years ago | on: Blacksmith – Rowhammer bit flips on all DRAM devices today despite mitigations
Google is working on platforms to make this easier to explore this problem, see https://opensource.googleblog.com/2021/11/Open%20source%20DD...
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Think of it like OHS Park for silicon!
You provide a 20mm2 design in the open source GF180MCU technology and you get back 1,000 parts. You can used an existing template or build something completely yourself with either open source or proprietary tooling (no required pad ring or management CPU).